A typical CMOS input stage is a conventional CMOS inverter which has a P channel and a N channel transistor in series between the positive and negative power supply terminals with the gates connected together to receive an input signal. When a CMOS integrated circuit is designed to receive TTL signals, the part must meet predetermined current and speed considerations for worst case TTL input conditions. A TTL signal may have a logic low with a voltage level as high as 0.8 volt. For high speed operation the CMOS transistors, both P and N, will have a threshold voltage of a magnitude significantly less than 0.8 volt, for example 0.5 volt. Consequently, the N channel transistor may be undesirably conducting even when the input signal is a logic low. This is an unwanted current drain. Conversely, the input signal may be a logic high with a voltage of only 2.0 volts. Because the supply voltage is typically about 5 volts, the input P channel device will be undesirably conducting, also causing an unwanted current drain. Consequently, the input N channel and P channel transistors must be sufficently large not only to charge and discharge the capacitance of the output node to obtain the desired speed but also large enough to handle the current undesirably supplied by the transistor which desirably would be non-conducting.